Single error correction-double error detection (“SECDED”) decoding may be used for decoding a string of bits, where error checking (“parity”) bits have been added to a set of data bits. SECDED codes for encoding information are also well known as “distance-4 Hamming codes.” A parity bit is any bit associated with one or more data bits for error checking a transmission of such data bits. Conventionally, parity bits are transmitted with data bits. “Error checking” may include both error detection and correction, or error detection without error correction.
For SECDED decoding, if any one bit, including data and parity bits, of a transmission is in error, the error can be detected and corrected; and if any two bits, including data bits, parity bits, or any combination of data and parity bits, of a transmission are in error, the error can be detected although it cannot be corrected.
With respect to configuring a programmable logic device, such as a Field Programmable Gate Array (“FPGA”), a configuration bitstream is transmitted to the FPGA. For configuring an FPGA, a bitstream frame of such a configuration bitstream may be in excess of a thousand bits, where bits are transmitted one word at a time. In other words, each bitstream frame is read one word at a time and not as a single thousand or more bit vector.
Accordingly, it would be both desirable and useful to provide error checking for bitstream frames transmitted one word at a time.